Field of the Invention
The present invention relates to a select gate of a non-volatile memory. More particularly, the present invention relates to a circuit and a method for adjusting a select gate voltage of a non-volatile memory.
Description of the Related Art
NAND flash memory is a popular kind of non-volatile memory. A NAND flash memory includes a plurality of blocks. Each block includes a plurality of NAND strings. Each NAND string includes a drain-side select transistor, a source-side select transistor, and multiple cell transistors in series between the two select transistors. Each cell transistor is a memory cell of the flash memory. Each select transistor has a select gate, while each cell transistor has a control gate and a floating gate.
FIG. 1 is a schematic diagram showing a cross section of a drain-side portion of a conventional NAND string. In FIG. 1, “SSL” represents the select gate of the drain-side select transistor. “CG” represents the control gates of the cell transistors. “FG” represents the floating gates of the cell transistors. “DMWL” represents the dummy word line. “WL31” and “WL30” represent two word lines of the flash memory. “PWI” represents the p-well of the NAND string.
As FIG. 1 shows, the drain-side select gate SSL has capacitive coupling with the neighboring dummy word line DMWL, the control gate CG and the floating gate FG under the dummy word line DMWL, and the p-well PWI.
Flash memories use Fowler—Nordheim (FN) tunneling from floating gates to p-well to erase flash cells, which decrease the number of electrons at the floating gates to lower their threshold voltage. To create FN tunneling bias condition, p-well is applied a high voltage (for example, 20V) and word line of memory cells is biased at low voltage (for example, 0V for the word lines, and 2V for edge dummy word lines).
In an erase operation, select gates are not supposed to be erased. Typically, select gates are floated so that they can be coupled high along with the p-well. The floating voltage of a select gate creates electric fields with the neighboring nodes. However, it is a trade-off about the final voltage of select gates.
If the select gate SSL is coupled to a high voltage due to the capacitive coupling between the select gate SSL and the neighboring p-well PWI, the vertical electric field (Ey) can be eased, yet a large horizontal electric field (Ex) exists between the neighboring floating gate FG and the select gate SSL. This might cause the electrons to tunnel out from the neighboring floating gate FG to inject to the channel under the space between the select gate SSL and the floating gate FG. The accumulation of these electrons over time will deplete the channel, increasing the threshold voltage of the select gate and decreasing cell “on” current. This is a concern of endurance for NAND flash memories.
If the select gate SSL is coupled to a relative low voltage, the vertical electric field (Ey) between the select gate SSL and the p-well PWI during erase operation would be larger. Such a vertical electric field stresses the oxide between the p-well PWI and the select gate SSL, inducing electrons to trap in the oxide. Electrons trapped in the oxide can affect string conductivity and cause reliability issue.
FIG. 2 is a schematic diagram showing a circuit 200 that is a part of a conventional NAND flash memory. The capacitor 206 represents the capacitive coupling between the select gate SSL and the p-well PWI of a NAND string of the NAND flash memory. The pass transistor 204 conducts the driving voltage GSSL to drive the select gate SSL. The pass transistor 204 is an n-channel metal-oxide-semiconductor field-effect transistor. The switch 202 provides the constant voltage 4V as the driving voltage GSSL. The switch 203 provides the constant voltage 0V as the driving voltage GSSL.
FIG. 3 is a timing diagram showing some voltage signals in the circuit 200 in an erase operation of the NAND flash memory. The voltage signals include the bias voltage PASS_GATE at the gate of the pass transistor 204, the driving voltage GSSL, the voltage of the select gate SSL, and the voltage of the p-well PWI.
Before t0 the switch 202 is opened and the switch 203 is closed. Therefore, GSSL is biased at 0V via the switch 203. At t0 the gate of the pass transistor 204 is biased at 4V. At t1 the switch 203 opens and the switch 202 closes and driving voltage GSSL is biased at 4V as well. As a result, the pass transistor 204 can pass the voltage (4V-VTN) to the select gate SSL. VTN is the threshold voltage of the pass transistor 204. Afterwards, the pass transistor 204 remains weakly on to keep the channel voltage at (4V-VTN).
The p-well PWI is applied a high erase voltage VERS (for example, 20V) in the erase operation. As FIG. 3 shows, the p-well PWI is charged to 20V at t2. At the same time the voltage of the select gate SSL rises up because of the capacitive coupling so as to cut off the pass transistor 204. The select gate SSL is coupled to high voltage along with the p-well PWI to reduce the voltage difference to the p-well PWI. In this duration, those word lines biased at low voltage use FN tunneling to remove electrons in floating gates. The dotted portion of the voltage of the select gate SSL in this duration represents the floating state of the select gate SSL caused by the turning off of the pass transistor 204 at t2.
The p-well PWI is discharged to ground at t3 and the select gate SSL is coupled to low voltage in the same way. When the voltage of the select gate SSL falls back to (4V-VTN), the pass transistor 204 becomes conductive again and drives the select gate SSL to the voltage level (4V-VTN).
By opening the switch 202 and closing the switch 203, the driving voltage GSSL starts to discharge at t4 and therefore the select gate SSL discharges as well. Finally, the pass transistor 204 is turned off at t5 and the erase operation is finished.
The voltage of the select gate SSL can be high enough to affect the endurance of the NAND flash memory. In this conventional scheme, the timing to float the select gate SSL cannot be freely decided, so that it is hard to adjust the final voltage (the highest voltage) of the select gate SSL through the capacitive coupling.